package fpga_generation.altera_onchip_memory;
import fpga_generation.java_base.*;

public class onchip_memory extends base_mm_slave
{
	int sizeInBytes;
	
	public onchip_memory(String name, int size)
	{
		super(name, "s1");
		this.type = "altera_avalon_onchip_memory2";
		this.clockSink = "clk1";
		this.sizeInBytes = size;
	}

	public void setDataWidth(int value) {

	}	
	
	public String writeRepr(int impl, int round) {
		String outputString = "";
		if (round == 0) {
			outputString += add_module(impl);
		}
		if (round == 1) {
		
			outputString += easyClockConnect();
		
			outputString += set_parameter(impl, "allowInSystemMemoryContentEditor", false);
			outputString += set_parameter(impl, "blockType", "AUTO");
			outputString += set_parameter(impl, "dataWidth", 32);
			outputString += set_parameter(impl, "dualPort", false);
			outputString += set_parameter(impl, "initMemContent", true);
			outputString += set_parameter(impl, "initializationFileName", "onchip_memory2_0");
			outputString += set_parameter(impl, "instanceID", "NONE");
			outputString += set_parameter(impl, "memorySize", 20000);
			outputString += set_parameter(impl, "readDuringWriteMode", "DONT_CARE");
			outputString += set_parameter(impl, "simAllowMRAMContentsFile", false);
			outputString += set_parameter(impl, "simMemInitOnlyFilename", 0);
			outputString += set_parameter(impl, "singleClockOperation", false);
			outputString += set_parameter(impl, "slave1Latency", 1);
			outputString += set_parameter(impl, "slave2Latency", 1);
			outputString += set_parameter(impl, "useNonDefaultInitFile", false);
			outputString += set_parameter(impl, "useShallowMemBlocks", false);
			outputString += set_parameter(impl, "writable", true);
		}
		return outputString;
	}

}